1. Field of the Invention
The present invention relates to a liquid crystal display device including an active panel, and more particularly, to a method of manufacturing a liquid crystal display device with low contact resistance between a drain electrode of the thin film transistor and the pixel electrode, and a method of manufacturing same.
2. Discussion of the Related Art
Thin film type flat panel display devices are often used in portable applications due to their light weight and easy adaptability. Research has focused on liquid crystal display devices (LCDs) because their high resolution and fast response time make them suitable for display of motion picture images.
A liquid crystal display device works by using polarized light and an optical anisotropy of a liquid crystal. By controlling orientation of rod-shaped liquid crystal molecules, transmission and interception of light through the liquid crystal are achieved due to the optical anisotropy of the liquid crystal. This principle is applied to the liquid crystal display device. Active Matrix Liquid Crystal Displays (AMLCDs) having thin film transistors (TFTs) arranged in a matrix pattern and pixel electrodes connected to the TFTs provide high quality images, and are now widely used. A structure of a conventional AMLCD will now be described.
Generally, a liquid crystal display device includes two panels facing each other with a liquid crystal material in between. The first panel (a color filter panel) of an LCD includes a sequential arrangement of red, blue and green color filters on a transparent substrate at pixel positions arranged in a matrix pattern. Among these color filters, black matrices are formed in a lattice pattern. A common electrode is formed on the color filters.
The second panel (an active panel) of the LCD includes pixel electrodes arranged in a matrix pattern and formed on a transparent substrate. Scan bus lines are arrayed along a column direction of the pixel electrodes, and data bus lines are arrayed along a row direction of the pixel electrodes. At a corner of each pixel, a TFT for driving the pixel electrode is formed. A gate electrode of the TFT is connected to the scan bus line (often referred to as a gate line). A source electrode of the TFT is connected to the data bus line (often referred to as a source line). A gate pad is formed at an end portion of each gate line, and a source pad is formed at an end portion of each source line.
The color filter panel and the active panel are bonded together facing each other with a certain distance between them (i.e., a cell gap). Liquid crystal material fills the cell gap, thus completing the liquid crystal panel of the LCD.
The method of manufacturing a simple liquid crystal display involves a combination of several processes. Manufacturing an active panel having TFTs and pixel electrodes involves additional steps. If the active panel has a shorting bar for probing the active panel, the manufacturing method is more complicated still. Therefore, it is important to simplify the manufacturing method of an active panel to reduce the possibility of defects during the manufacture process.
A conventional method for manufacturing an active panel having a shorting bar will be described with reference to FIG. 1, which shows a plan view of an active panel and FIGS. 2A-2F, which show cross-sectional views taken along line II--II of FIG. 1.
Aluminum or an aluminum alloy is deposited on a substrate 1, such as a transparent non-alkalic glass substrate, to form a thin aluminum layer. A low resistance gate line 13a is formed by patterning the thin aluminum layer using a first mask process. The low resistance gate line 13a extends along a row direction of a pixel array, which is arranged in a matrix, as shown in FIGS. 1 and 2A.
A metal layer, including one of chromium, molybdenum, tantalum, or antimony, is deposited on the substrate 1 and the low resistance gate layer 13a (not shown in FIGS. 1 and 2A). A gate electrode 11 and a gate line 13 are formed by patterning the metal layer using a second mask process. The gate line 13 covers the low resistance gate line 13a. The gate electrode 11 is derived from the gate line 13 and is formed at one corner of the pixel, as shown in FIG. 2B.
As shown in FIG. 2C, first inorganic material, such as silicon nitride or silicon oxide, is deposited on the substrate 1 and the gate line 13 to form a gate insulation layer 17. An intrinsic semiconductor material, such as pure amorphous silicon, and an extrinsic semiconductor material, such as impurity doped amorphous silicon, are sequentially deposited thereon. A semiconductor layer 33 and a doped semiconductor layer 35 are formed by patterning the intrinsic and extrinsic semiconductor materials by using a third mask process.
FIG. 2D illustrates that a chromium layer is deposited on the substrate and the doped semiconductor layer 35. A source electrode 21, a drain electrode 31, a storage capacitor electrode 51 and a source line 23 are formed by patterning the chromium layer using a fourth mask process. The source electrode 21 overlaps one side of the gate electrode 11, with the semiconductor layer 33 and the doped semiconductor 35 sandwiched in between. The drain electrode 31 faces the source electrode 21 and overlaps another side of the gate electrode 11. The source line 23 connects to the source electrode 21, a plurality of which will be arrayed in a column direction. The doped semiconductor layer 35 is separated into two parts using the source electrode 21 and the drain electrode 31 as a mask. The doped semiconductor layer 35 is an ohmic contact to the source electrode 21 and the drain electrode 31. The storage capacitor electrode 51 overlaps a portion of the gate line 13, with the gate insulation layer 17 below the storage capacitor electrode 21. The storage capacitor electrode 51 and the overlapped portion of the gate line 13 form a storage capacitor to compensate for leakage of charge stored in the liquid crystal capacitor, as shown in FIG. 2D.
A passivation layer 37 is formed by coating an organic insulation material such as BCB (Benzo-Cyclo-Butene) over the entire structure. A drain contact hole 71 and a storage capacitor contact hole 81 are formed by patterning the passivation layer 37 using a fifth mask process. The drain contact hole 71 exposes a portion of a surface of the drain electrode 31, and the storage capacitor contact hole 81 exposes a portion of a surface of the storage capacitor electrode 51, as shown in FIG. 2E.
An ITO (Indium Tin Oxide) layer is deposited on the passivation layer 37 and patterned to form a pixel electrode 41 by using a sixth mask process. The pixel electrode 41 connects to the drain electrode 31 through the drain contact hole 71 and connects to the storage capacitor electrode 51 through the storage capacitor contact hole 81, as shown in FIG. 2F. Therefore, charge stored in the storage capacitor formed by overlapping the storage capacitor electrode 51 and the portion of the gate line 13 leaks out over time.
In the conventional LCD, the passivation layer 37 comprises an organic material such as BCB in order to get a high aperture ratio. Generally, an etchant including a fluorine ion (F.sup.-) is used for etching the organic material to form the drain contact hole 71 and the storage capacitor contact hole 81. Exposed portions of the drain electrode 31 and the storage capacitor electrode 51 can be etched by the etchant having the fluorine ion (F.sup.-). Therefore, etched sides of the drain electrode 31 and the storage capacitor electrode 51, rather than their surfaces, are exposed through the contact holes 71 and 81. After that, ITO is deposited thereon to form the pixel electrode 41. The etched sides of the drain electrode 31 and the storage capacitor electrode 51 are in contact with the pixel electrode 41, as shown in FIGS. 3A and 3B.
The storage contact hole 81 is large enough to maintain normal contact, as shown in FIG. 3B, and contact resistance remains low. However, the drain contact hole 71 is very small, as shown in FIG. 3A. When the etched side of the drain electrode 31 is in contact with the pixel electrode 41, contact resistance is high because the contact area is too small. Therefore, electrical signal voltage representing an image may not be properly applied to the pixel electrode 41, resulting in an uneven quality of the image.
Characteristics of the TFT of an LCD representing a horizontal dark stripe on the screen were measured. The LCD had a 12.1 inch display area and included a BCB material as a passivation layer. The result showed that there is a problem in the current output curve between the source electrode 21 and the pixel electrode 41 of the TFT corresponding to the horizontal dark line. A calculation of the resistance of the drain electrode 31 shows that the resistance should be less than 1.5M.OMEGA. in order to avoid the horizontal dark stripe. If the resistance is larger than 3M.OMEGA., a horizontal dark stripe will appear. Thus, one reason for the unevenness of the displayed image is high resistance of the drain electrode 31 resulting from the high contact resistance between the drain and pixel electrodes 31 and 41.